FIG. 1 illustrates a prior art electrically erasable programmable read only memory cell, as illustrated and described in Fabrication and Characterization of a New EEPROM Cell With Spacer Select Transistor, by Junghwan Lee et al., IEEE Electron Device Letters, Vol. 26, No. 8, August 2005, which article is hereby incorporated by reference in its entirety.
As described in Junghwan Lee et al., the cell has spacer select gates (labelled as “control gate” in FIG. 1) on both side walls of floating gate, which helps result in a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 μm2 with 0.18 μm logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. Programming requires 3 ms at 16 V, while erasing requires 2 ms at 14 V. The operating voltages for selected and unselected cells are shown in Table 1.
TABLE 1Bias condition during programming (writing), erasing, and reading, for bothselected and unselected cells configured as shown in FIG. 1.Program/WriteEraseReadControl GateSelected16 V  0 V2.5 V  Unselected2.5 V  11 V0 VBit LineSelected0 V14 V1.0 V  Unselected12 V 11 V0 VP-WellSelected0 V14 V0 VUnselected0 V 0 V0 VSourceSelectedFloatingFloating0 VUnselectedFloatingFloating0 V
As illustrated by Table 1, the junctions of this known cell operate at relatively high voltages (12V-16V). This means that the junctions underneath the control gate spacers (control gate) are relatively large and deep, and the gate oxide under the gate spacers (control gate) is relatively thick, in particular much thicker than the tunnel oxide underneath the floating gate. This relatively large thickness of the control gate oxide resists the flow of read current, such that the dimension of the cell into the page must be kept relatively large. Thus, the size of this memory cell cannot be easily scaled down to smaller geometries, while still providing sufficient read current.